SyllabusTranslating Pure Esterel v5 into Inter-operability Relationships Between Esterel & VHDL Relationships Between Esterel & VHDL in an Instant What about Esterel? VHDL Overview Main features of the selected VHDL subset VHDL Example: VHDL Example: How Run the Only Active Parts? Reaction to Signal Absence? Summary of issues Chosen Inner Format Interpreting GRC Constructions Into VHDL A Simple Esterel Program ABO Into GRC Translation Workflow Control Flow Dispatching Concurrency, Sequence and Causality Reaction to Absence Algorithm Overview Absence in VHDL Conclusion Future Work |
Author:Bertrand B. Blanc E-mail: Bertrand.Blanc@cma.inria.fr Download the presentation (ZIP MS-PPT 187KB) Download the presentation (PDF 529KB)) |